1. Field of the Invention
The present invention relates to methods and apparatus for communicating digital data as serial data in time series representing logical values of respective bits of the digital data.
2. Description of the Related Art
Clock-synchronized communication has been well-known heretofore as a method of transmitting and receiving serial data expanded to a time series from digital data. In clock-synchronized communication, the transmitting end transmits, through separate transmission paths, a clock signal indicating breaks between respective bits, and a data signal synchronized with the clock signal, while the receiving end takes in the data signal at points of time synchronized with the incoming clock signal.
Clock-synchronized communication has no limitation to transmission speed insofar as the receiving device is capable of receiving the transmit signals. It is also possible to vary transmission speed in the course of signal transmission only if the data signal remains synchronized with the transmission clock signal. Clock-synchronized communication, little restricted in terms of transmission speed as noted above, is realized with software and widely used in systems employing one-chip microcomputers and the like having general-purpose input/output (I/O) ports.
FIG. 5A shows one example of conventional systems designed for clock-synchronized communication. In clock-synchronized communication, I/O interfaces of a transmitting device 1 and a receiving device 2 are interconnected by a data signal line 3 seerving as a transmission path of data signals, and a clock signal line 4 serving as a transmission path of clock signals.
FIG. 5B shows an example of transmit data and examples of data signals and clock signals used in a conventional method of clock-synchronized communication. In FIG. 5B, logical value "1" is applied to the high voltage level of the signals, and logical value "0" to the low voltage level.
The transmitting device 1 varies or holds a logical value of the data signal in synchronism with a change from high level to low level (also called "fall" hereinafter) of the clock signal, and maintains the value of the data signal until a next fall of the clock signal. Subsequently, upon a lapse of a predetermined time, the clock signal changes from low level to high level (which change is also called "rise" hereinafter). The above sequence is repeated after a further predetermined time, which is continued until completion of the data transmission.
The receiving device 2 constantly reads the values of the clock signals transmitted through the clock signal line 4. The receiving device 2 takes in the values of the data signal at rises of the clock signals, which is continued until completion of the data reception.
There is also a method opposite to the example shown in FIG. 5B. In this method, the transmitting device successively transmits bit data in synchronism with rises of the transmission clock signals, while the receiving device takes in the data at falls of the clock signals.
FIG. 6 shows a method of serial communication disclosed in JP-A 8-163182(1996). This method employs two signal forms, i.e. form 1 and form 2, corresponding to each of sign "0" and sign "1" used in communication. Form 1 and form 2 of sign "0" take the high signal level and the low signal level, respectively. Form 1 and form 2 of sign "1" alternately take the high signal level and the low signal level. A high-level period of form 1 for sign "0", a low-level period of form 2 for sign "0", a sum of one high-level period and one low-level period of form 1 for sign "1" and a sum of one low-level period and one high-level period of form 2 for sign "1" are all controlled to equal a minimum unit communication time provided by the system. This method of serial communication facilitates a bit-by-bit synchronization since a clock signal is superposed on a data signal.
To transmit 1-bit data in the conventional clock-synchronized communication, the data signal needs to be changed only once, but the clock signal must be changed from high level to low level and, after the predetermined time, from low level to high level. That is, a communication of 1-bit data requires the clock signal to be changed twice.
On the other hand, the receiving end, constantly reading the values of the clock signals during reception, must confirm a change of the clock signal from high level to low level, and then read a change of the clock signal to high level. That is, two changes of the clock signal must be read for receiving 1-bit data.
As described above, the conventional clock-synchronized communication has the clock signal changing twice in transmitting and receiving 1-bit data. Where these changes are processed by software, using general-purpose I/O ports provided for one-chip microcomputers or the like, an operation for reading the two changes of the clock signal consumes a longer processing time than the case of reading only one change of the clock signal. Consequently, an acceptable transmission speed is restricted by a maximum rate at which the receiving end can read the clock signal.
Where transmission and reception of the clock signal are carried out with CMOS devices, power consumption by the CMOS devices increases with an increase in the frequency of the clock signal. Further, since the data signal is synchronized with the clock signal, a data communication once started must be continued until a series of data to be communicated has been transmitted and received.
In the method of serial communication disclosed in JP-A 8-163182(1996), 1-bit data is received by reading only one change of the data signal for either one of the logical values. However, it is necessary to read two changes of the data signal for the other logical value as in the conventional clock-synchronized communication.